The present invention relates generally to the area of automated very large scale integrated circuit technology. More particularly, it relates to the optimized design of Differential Cascode Voltage Switch (DCVS) logic trees implemented in complementary metal oxide semiconductor (CMOS) technology. It relates still more particularly to a method for improving the wirability, reliability and ease of manufacture of such circuits.
Differential cascode voltage switch (DCVS) trees are high performance, high functionality CMOS circuits, which, because they have a large number of inputs and internal connections are difficult to wire on a large scale.
Differential cascode voltage switch circuits are formed by decomposing logic into a set of interrelated Boolean expressions, each of which is implemented as a binary decision tree of interconnected differential pairs. A differential pair comprises a pair of transistors with differential inputs and common source. The input to each pair is a differential signal which switches on one of the transistors. The result is the creation of a unique conducting path through the tree. The tree output signals indicate the true and complement values of the Boolean function which has the control signals as its variables.
DCVS trees are typically assembled from n-channel differential pairs and p-channel loads. For a discussion of DCVS tree design, the following two references may be referred to for background information.
[1] L. G. Heller, W. R. Griffin, J. W. Davis and N. G. Thoma, "Cascode Voltage Switch Logic: A Differential CMOS Logic Family," 31st IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 1984, pp. 16-17.
[2] C. K. Erdelyi, W. P. Griffin and R. D. Kilmoyer, "Cascode Voltage Switch Logic Design," VLSI Design, v. V, 1984, pp. 78-86.
The logic designer, or design program, can synthesize logic by constructing from these elements the particular set of trees which leads to the most efficient design. Trees make extensive use of internal dotting, and thus make powerful circuits, such as XORs and parity trees. The number of stages and the associated delay decrease in direct proportion to the functionality of the trees. Because of the diversity of functions which can be synthesized, DCVS combines the simplicity of having a small number of basic circuit elements with the efficiency of design afforded by a large circuit library.
As noted above, the functional power of DCVS trees derives from the dotting provided by the extensive interconnection of the transistor pairs. The price paid for this otherwise free computing power is local congestion near the transistor pairs. When all wiring shares the same tracks, this congestion impedes the wiring of the gate input signals, which originate from other trees. One of the hallmarks of DCVS logic is the large number of input variables associated with each tree. Moreover, the true and complement of each variable occur as distinct nets, and these nets typically have large fanout within a macro design. The two factors of dense global and internal tree wiring combine to limit the achievable circuit density for all but relatively small DCVS macros.
The key to obtaining high densities with DCVS is to remove or reduce the congestion caused by the complex internal tree wiring and to maximize the efficiency of wiring the differential inputs of the transistor pairs.
Previous attempts to improve the wirability of DCVS trees has involved the local customization of the trees in which their structures are changed so as to simplify global wiring. There was also some consideration given to complexity of internal tree wiring, but in practice, the global considerations override any of those considerations. The present invention does simplify internal wiring in a direct and telling manner.
The previous technique involves logical recon firguration and is referenced in the subsequent prior art section. (IBM Technical Disclosure Bulletin article Vol. 27, No. 3, Aug. 84).
As stated previously, DCVS chips are difficult to wire because of the high density of contacts. For many images, DCVS trees are allotted a fixed area, called a tree accounting area (TAA). For small collections of trees, all connections, internal and external to the trees, are wirable in two levels of metal, with wiring space (porosity) left over. As practical sizes are approached, the porosity decreases until a size is reached where all the wiring space is used, and the design becomes unwirable. In standard cell designs, some of the internal (source-drain) connections are wired in diffusion, decreasing the metal-wire space usage.
There is, accordingly, continuous pressure on logic and chip design professionals to provide improved design tools which will increase the wirability of DCVS logic trees and thus achieve the highest possible density of resultant chips.